The current computing landscape has witnessed a rapid and ongoing surge of change and innovation. This change has been driven by the relentless need to improve the energy-efficiency, memory, and computational throughput across all levels of the architectural hierarchy. The mounting volume of data that today's systems need to organize poses new challenges to the architecture, which can no longer be solved with classical, homogeneous designs. Advancements in all these areas have led Heterogeneous systems to become the norm rather than the exception.

Heterogeneous computing leverages a diverse set of computing (CPU, GPU, FPGA, TPU, DPU, etc.) and Memory (HBM, Persistent Memory, Coherent PCI protocols, etc.), hierarchical systems, and units to accelerate the execution of a diverse set of applications. Emerging and existing areas such as AI, BigData, Cloud Computing, Edge-Computing, Real-time systems, High-Performance Computing, and others have seen a real benefit due to Heterogeneous computer architectures. In addition, a new wave of accelerators based on dataflow architecture instead of the traditional von Neumann is sure to bring additional challenges and opportunities.

These new heterogeneous architectures often also require the development of new applications and programming models, to satisfy these new architectures and to fully utilize their capabilities. This workshop focuses on understanding the implications of heterogeneous designs at all levels of the computing system stack, such as hardware, compiler optimizations, porting of applications, and developing programming environments for current and emerging systems in all the above-mentioned areas. It seeks to ground heterogeneous system design research through studies of application kernels and/or whole applications, as well as shed light on new tools, libraries, and runtime systems that improve the performance and productivity of applications on heterogeneous systems.

The goal of this workshop is to bring together researchers and practitioners who are at the forefront of Heterogeneous computing to learn the opportunities and challenges in future Heterogeneous system design trends and thus help influence the next trends in this area.

Topics of interest include (but are not limited to):

Applications for GPU-based systems, and hybrid/heterogeneous systems

• Applications leveraging GPUs, FPGAs, TPUs, DPUs, and On-Chip Accelerators
• AI/ML workloads including generative AI training/inference (e.g. LLMs, LDMs), recommendation systems and AI for science and engineering
• Scientific and engineering applications
• Big data and cloud computing workloads
• Edge computing and real-time applications
• Application behavior characterization and performance analysis
• Domain-specific applications and benchmarks

Systems Architecture and Design

• Heterogeneous system architectures (ARM, RISC-V, custom extensions)
• Memory hierarchies and novel memory systems
• Energy efficiency and thermal considerations
• Security and reliability in heterogeneous systems
• Design space exploration and trade-off analysis
• Performance modeling and prediction
• Emerging accelerator architectures (dataflow, neuromorphic, etc.)

Programming Models and Development Tools

• High-level programming models (OpenMP, OpenACC, SYCL, OneAPI, Kokkos, Raja)
• Low-level programming interfaces (OpenCL, CUDA)
• Debugging and profiling tools
• Performance optimization and autotuning frameworks
• Testing and verification methods for heterogeneous systems
• Workload characterization tools
• Benchmarking suites and methodologies

Heterogeneous System Software and Runtime Systems

• Compiler optimizations for heterogeneous systems
• Runtime systems and resource management
• Operating system support for heterogeneous computing
• Virtualization and containerization for heterogeneous systems
• Task scheduling and load balancin
• Memory management and data movement optimization
• System-level monitoring and telemetry
• Integration of heterogeneous components and interfaces
• Communication software/middleware for heterogeneous systems

Paper Tracks:

There are two paper tracks available for AsHES’25:

• 1) Full paper track (10 pages) including citations;
• 2) Short paper track (maximum of 4 pages) including citations; meant to highlight early investigations of innovative ideas.

Submitted papers will undergo a single-blind review process, so the authors do not need to anonymize a submission.

Paper Submission: January 17, 2025

Paper Notification: February 17, 2025

Camera-ready Deadline: March 6th, 2025

The best paper will receive a certificate of recognition. This award will be given based on the paper's originality, impact, and overall quality

The proceedings of this workshop will be published electronically together with IPDPS proceedings via the IEEE Xplore Digital Library.

Papers should present original research and should provide sufficient background material to make them accessible to the broader community.

Regular paper track submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references. See the style templates for latex or word for details.

Short paper track submitted manuscripts follow the same instructions as the regular manuscript but may not exceed 4 pages.

Submissions will be judged based on relevance, significance, originality, correctness, and clarity.

Submission site: https://easychair.org/conferences/?conf=ashes2025

TBD

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